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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a> &#124;
<a href="#var-members">Variables</a>  </div>
  <div class="headertitle">
<div class="title">CMSIS Core Instruction Interface</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a>&#160;&#160;&#160;__nop</td></tr>
<tr class="memdesc:gabd585ddc865fb9b7f2493af1eee1a572"><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#gabd585ddc865fb9b7f2493af1eee1a572">More...</a><br /></td></tr>
<tr class="separator:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gad23bf2b78a9a4524157c9de0d30b7448">__WFI</a>&#160;&#160;&#160;__wfi</td></tr>
<tr class="memdesc:gad23bf2b78a9a4524157c9de0d30b7448"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gad23bf2b78a9a4524157c9de0d30b7448">More...</a><br /></td></tr>
<tr class="separator:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d">__WFE</a>&#160;&#160;&#160;__wfe</td></tr>
<tr class="memdesc:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gaac6cc7dd4325d9cb40d3290fa5244b3d">More...</a><br /></td></tr>
<tr class="separator:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaab4f296d0022b4b10dc0976eb22052f9">__SEV</a>&#160;&#160;&#160;__sev</td></tr>
<tr class="memdesc:gaab4f296d0022b4b10dc0976eb22052f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#gaab4f296d0022b4b10dc0976eb22052f9">More...</a><br /></td></tr>
<tr class="separator:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad233022e850a009fc6f7602be1182f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaad233022e850a009fc6f7602be1182f6">__ISB</a>()</td></tr>
<tr class="memdesc:gaad233022e850a009fc6f7602be1182f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#gaad233022e850a009fc6f7602be1182f6">More...</a><br /></td></tr>
<tr class="separator:gaad233022e850a009fc6f7602be1182f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga067d257a2b34565410acefb5afef2203"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>()</td></tr>
<tr class="memdesc:ga067d257a2b34565410acefb5afef2203"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#ga067d257a2b34565410acefb5afef2203">More...</a><br /></td></tr>
<tr class="separator:ga067d257a2b34565410acefb5afef2203"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga671101179b5943990785f36f8c1e2269"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga671101179b5943990785f36f8c1e2269">__DMB</a>()</td></tr>
<tr class="memdesc:ga671101179b5943990785f36f8c1e2269"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#ga671101179b5943990785f36f8c1e2269">More...</a><br /></td></tr>
<tr class="separator:ga671101179b5943990785f36f8c1e2269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14f54807872c0f5e05604c4924abfdae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga14f54807872c0f5e05604c4924abfdae">__REV</a>&#160;&#160;&#160;__rev</td></tr>
<tr class="memdesc:ga14f54807872c0f5e05604c4924abfdae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#ga14f54807872c0f5e05604c4924abfdae">More...</a><br /></td></tr>
<tr class="separator:ga14f54807872c0f5e05604c4924abfdae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95b9bd281ddeda378b85afdb8f2ced86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga95b9bd281ddeda378b85afdb8f2ced86">__ROR</a>&#160;&#160;&#160;__ror</td></tr>
<tr class="memdesc:ga95b9bd281ddeda378b85afdb8f2ced86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate Right in unsigned value (32 bit)  <a href="#ga95b9bd281ddeda378b85afdb8f2ced86">More...</a><br /></td></tr>
<tr class="separator:ga95b9bd281ddeda378b85afdb8f2ced86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga15ea6bd3c507d3e81c3b3a1258e46397">__BKPT</a>(value)&#160;&#160;&#160;__breakpoint(value)</td></tr>
<tr class="memdesc:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Breakpoint.  <a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">More...</a><br /></td></tr>
<tr class="separator:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga5d5bb1527e042be4a9fa5a33f65cc248">__CLZ</a>&#160;&#160;&#160;__clz</td></tr>
<tr class="memdesc:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros.  <a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">More...</a><br /></td></tr>
<tr class="separator:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc17e391c13c71702366c67cba39c276"><td class="memItemLeft" align="right" valign="top"><a id="gabc17e391c13c71702366c67cba39c276"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__CMSIS_GCC_OUT_REG</b>(r)&#160;&#160;&#160;&quot;=r&quot; (r)</td></tr>
<tr class="separator:gabc17e391c13c71702366c67cba39c276"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d94dee7402367961d2cf0accc00fd97"><td class="memItemLeft" align="right" valign="top"><a id="ga9d94dee7402367961d2cf0accc00fd97"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__CMSIS_GCC_USE_REG</b>(r)&#160;&#160;&#160;&quot;r&quot; (r)</td></tr>
<tr class="separator:ga9d94dee7402367961d2cf0accc00fd97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a>&#160;&#160;&#160;__builtin_arm_nop</td></tr>
<tr class="memdesc:gabd585ddc865fb9b7f2493af1eee1a572"><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#gabd585ddc865fb9b7f2493af1eee1a572">More...</a><br /></td></tr>
<tr class="separator:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gad23bf2b78a9a4524157c9de0d30b7448">__WFI</a>&#160;&#160;&#160;__builtin_arm_wfi</td></tr>
<tr class="memdesc:gad23bf2b78a9a4524157c9de0d30b7448"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gad23bf2b78a9a4524157c9de0d30b7448">More...</a><br /></td></tr>
<tr class="separator:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d">__WFE</a>&#160;&#160;&#160;__builtin_arm_wfe</td></tr>
<tr class="memdesc:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gaac6cc7dd4325d9cb40d3290fa5244b3d">More...</a><br /></td></tr>
<tr class="separator:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaab4f296d0022b4b10dc0976eb22052f9">__SEV</a>&#160;&#160;&#160;__builtin_arm_sev</td></tr>
<tr class="memdesc:gaab4f296d0022b4b10dc0976eb22052f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#gaab4f296d0022b4b10dc0976eb22052f9">More...</a><br /></td></tr>
<tr class="separator:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad233022e850a009fc6f7602be1182f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaad233022e850a009fc6f7602be1182f6">__ISB</a>()&#160;&#160;&#160;__builtin_arm_isb(0xF);</td></tr>
<tr class="memdesc:gaad233022e850a009fc6f7602be1182f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#gaad233022e850a009fc6f7602be1182f6">More...</a><br /></td></tr>
<tr class="separator:gaad233022e850a009fc6f7602be1182f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga067d257a2b34565410acefb5afef2203"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>()&#160;&#160;&#160;__builtin_arm_dsb(0xF);</td></tr>
<tr class="memdesc:ga067d257a2b34565410acefb5afef2203"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#ga067d257a2b34565410acefb5afef2203">More...</a><br /></td></tr>
<tr class="separator:ga067d257a2b34565410acefb5afef2203"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga671101179b5943990785f36f8c1e2269"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga671101179b5943990785f36f8c1e2269">__DMB</a>()&#160;&#160;&#160;__builtin_arm_dmb(0xF);</td></tr>
<tr class="memdesc:ga671101179b5943990785f36f8c1e2269"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#ga671101179b5943990785f36f8c1e2269">More...</a><br /></td></tr>
<tr class="separator:ga671101179b5943990785f36f8c1e2269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca25a02e09983da5558f5242f2f635bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaca25a02e09983da5558f5242f2f635bc">__REV</a>(value)&#160;&#160;&#160;__builtin_bswap32(value)</td></tr>
<tr class="memdesc:gaca25a02e09983da5558f5242f2f635bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#gaca25a02e09983da5558f5242f2f635bc">More...</a><br /></td></tr>
<tr class="separator:gaca25a02e09983da5558f5242f2f635bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad35497777af37e7809271b5e6f9510ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gad35497777af37e7809271b5e6f9510ba">__REV16</a>(value)&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab16acb6456176f1e87a4f2724c2b6028">__ROR</a>(<a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gadb92679719950635fba8b1b954072695">__REV</a>(value), 16)</td></tr>
<tr class="memdesc:gad35497777af37e7809271b5e6f9510ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gad35497777af37e7809271b5e6f9510ba">More...</a><br /></td></tr>
<tr class="separator:gad35497777af37e7809271b5e6f9510ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae580812686119c9c5cf3c11a7519a404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gae580812686119c9c5cf3c11a7519a404">__REVSH</a>(value)&#160;&#160;&#160;(int16_t)__builtin_bswap16(value)</td></tr>
<tr class="memdesc:gae580812686119c9c5cf3c11a7519a404"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gae580812686119c9c5cf3c11a7519a404">More...</a><br /></td></tr>
<tr class="separator:gae580812686119c9c5cf3c11a7519a404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga15ea6bd3c507d3e81c3b3a1258e46397">__BKPT</a>(value)&#160;&#160;&#160;__ASM volatile (&quot;bkpt &quot;#value)</td></tr>
<tr class="memdesc:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Breakpoint.  <a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">More...</a><br /></td></tr>
<tr class="separator:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab83768933a612816fad669db5488366f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab83768933a612816fad669db5488366f">__RBIT</a>&#160;&#160;&#160;__builtin_arm_rbit</td></tr>
<tr class="memdesc:gab83768933a612816fad669db5488366f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value.  <a href="#gab83768933a612816fad669db5488366f">More...</a><br /></td></tr>
<tr class="separator:gab83768933a612816fad669db5488366f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga5d5bb1527e042be4a9fa5a33f65cc248">__CLZ</a>&#160;&#160;&#160;(uint8_t)__builtin_clz</td></tr>
<tr class="memdesc:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros.  <a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">More...</a><br /></td></tr>
<tr class="separator:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc17e391c13c71702366c67cba39c276"><td class="memItemLeft" align="right" valign="top"><a id="gabc17e391c13c71702366c67cba39c276"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>__CMSIS_GCC_OUT_REG</b>(r)&#160;&#160;&#160;&quot;=r&quot; (r)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>__CMSIS_GCC_RW_REG</b>(r)&#160;&#160;&#160;&quot;+r&quot; (r)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>__CMSIS_GCC_USE_REG</b>(r)&#160;&#160;&#160;&quot;r&quot; (r)</td></tr>
<tr class="separator:ga9d94dee7402367961d2cf0accc00fd97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b13f3617dd4af2cd2eb3a311073f717"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga0b13f3617dd4af2cd2eb3a311073f717">__NOP</a>()&#160;&#160;&#160;__ASM volatile (&quot;nop&quot;)</td></tr>
<tr class="memdesc:ga0b13f3617dd4af2cd2eb3a311073f717"><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#ga0b13f3617dd4af2cd2eb3a311073f717">More...</a><br /></td></tr>
<tr class="separator:ga0b13f3617dd4af2cd2eb3a311073f717"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab28e2b328c4cf23c917ab18a23194f8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab28e2b328c4cf23c917ab18a23194f8e">__WFI</a>()&#160;&#160;&#160;__ASM volatile (&quot;wfi&quot;)</td></tr>
<tr class="memdesc:gab28e2b328c4cf23c917ab18a23194f8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gab28e2b328c4cf23c917ab18a23194f8e">More...</a><br /></td></tr>
<tr class="separator:gab28e2b328c4cf23c917ab18a23194f8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0330712223f4cfb6091e4ab84775f73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaf0330712223f4cfb6091e4ab84775f73">__WFE</a>()&#160;&#160;&#160;__ASM volatile (&quot;wfe&quot;)</td></tr>
<tr class="memdesc:gaf0330712223f4cfb6091e4ab84775f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gaf0330712223f4cfb6091e4ab84775f73">More...</a><br /></td></tr>
<tr class="separator:gaf0330712223f4cfb6091e4ab84775f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa58e60fcd2176ad58f96947466ea1fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gafa58e60fcd2176ad58f96947466ea1fa">__SEV</a>()&#160;&#160;&#160;__ASM volatile (&quot;sev&quot;)</td></tr>
<tr class="memdesc:gafa58e60fcd2176ad58f96947466ea1fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#gafa58e60fcd2176ad58f96947466ea1fa">More...</a><br /></td></tr>
<tr class="separator:gafa58e60fcd2176ad58f96947466ea1fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga15ea6bd3c507d3e81c3b3a1258e46397">__BKPT</a>(value)&#160;&#160;&#160;__ASM volatile (&quot;bkpt &quot;#value)</td></tr>
<tr class="memdesc:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Breakpoint.  <a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">More...</a><br /></td></tr>
<tr class="separator:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga5d5bb1527e042be4a9fa5a33f65cc248">__CLZ</a>&#160;&#160;&#160;(uint8_t)__builtin_clz</td></tr>
<tr class="memdesc:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros.  <a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">More...</a><br /></td></tr>
<tr class="separator:ga5d5bb1527e042be4a9fa5a33f65cc248"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gae84a2733711339c5eefeb0d899506b96"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gae84a2733711339c5eefeb0d899506b96">__attribute__</a> ((section(&quot;.rev16_text&quot;))) __STATIC_INLINE __ASM uint32_t <a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaa12aedd096506c9639c1581acd5c6a78">__REV16</a>(uint32_t value)</td></tr>
<tr class="memdesc:gae84a2733711339c5eefeb0d899506b96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gae84a2733711339c5eefeb0d899506b96">More...</a><br /></td></tr>
<tr class="separator:gae84a2733711339c5eefeb0d899506b96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe2b619a40cc0a7ffa8f765249ccf682"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gabe2b619a40cc0a7ffa8f765249ccf682">__attribute__</a> ((section(&quot;.revsh_text&quot;))) __STATIC_INLINE __ASM int16_t <a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gacb695341318226a5f69ed508166622ac">__REVSH</a>(int16_t value)</td></tr>
<tr class="memdesc:gabe2b619a40cc0a7ffa8f765249ccf682"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gabe2b619a40cc0a7ffa8f765249ccf682">More...</a><br /></td></tr>
<tr class="separator:gabe2b619a40cc0a7ffa8f765249ccf682"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab926fe7178a379c3a7c0410b06fcb661"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab926fe7178a379c3a7c0410b06fcb661">__attribute__</a> ((always_inline)) __STATIC_INLINE uint32_t <a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaf944a7b7d8fd70164cca27669316bcf7">__RBIT</a>(uint32_t value)</td></tr>
<tr class="memdesc:gab926fe7178a379c3a7c0410b06fcb661"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value.  <a href="#gab926fe7178a379c3a7c0410b06fcb661">More...</a><br /></td></tr>
<tr class="separator:gab926fe7178a379c3a7c0410b06fcb661"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab16acb6456176f1e87a4f2724c2b6028"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab16acb6456176f1e87a4f2724c2b6028">__ROR</a> (uint32_t op1, uint32_t op2)</td></tr>
<tr class="memdesc:gab16acb6456176f1e87a4f2724c2b6028"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate Right in unsigned value (32 bit)  <a href="#gab16acb6456176f1e87a4f2724c2b6028">More...</a><br /></td></tr>
<tr class="separator:gab16acb6456176f1e87a4f2724c2b6028"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga372c0535573dde3e37f0f08c774a3487"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga372c0535573dde3e37f0f08c774a3487">__SSAT</a> (int32_t val, uint32_t sat)</td></tr>
<tr class="memdesc:ga372c0535573dde3e37f0f08c774a3487"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signed Saturate.  <a href="#ga372c0535573dde3e37f0f08c774a3487">More...</a><br /></td></tr>
<tr class="separator:ga372c0535573dde3e37f0f08c774a3487"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6562dbd8182d1571e22dbca7ebdfa9bc"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga6562dbd8182d1571e22dbca7ebdfa9bc">__USAT</a> (int32_t val, uint32_t sat)</td></tr>
<tr class="memdesc:ga6562dbd8182d1571e22dbca7ebdfa9bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsigned Saturate.  <a href="#ga6562dbd8182d1571e22dbca7ebdfa9bc">More...</a><br /></td></tr>
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<tr class="memitem:gae26c2b3961e702aeabc24d4984ebd369"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gae26c2b3961e702aeabc24d4984ebd369">__ISB</a> (void)</td></tr>
<tr class="memdesc:gae26c2b3961e702aeabc24d4984ebd369"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#gae26c2b3961e702aeabc24d4984ebd369">More...</a><br /></td></tr>
<tr class="separator:gae26c2b3961e702aeabc24d4984ebd369"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fe277f5385d23b9c44b2cbda1577ce9"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#ga7fe277f5385d23b9c44b2cbda1577ce9">__DSB</a> (void)</td></tr>
<tr class="memdesc:ga7fe277f5385d23b9c44b2cbda1577ce9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#ga7fe277f5385d23b9c44b2cbda1577ce9">More...</a><br /></td></tr>
<tr class="separator:ga7fe277f5385d23b9c44b2cbda1577ce9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1ea24daaaaee9c828f90cbca330cb5e"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab1ea24daaaaee9c828f90cbca330cb5e">__DMB</a> (void)</td></tr>
<tr class="memdesc:gab1ea24daaaaee9c828f90cbca330cb5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#gab1ea24daaaaee9c828f90cbca330cb5e">More...</a><br /></td></tr>
<tr class="separator:gab1ea24daaaaee9c828f90cbca330cb5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb92679719950635fba8b1b954072695"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gadb92679719950635fba8b1b954072695">__REV</a> (uint32_t value)</td></tr>
<tr class="memdesc:gadb92679719950635fba8b1b954072695"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#gadb92679719950635fba8b1b954072695">More...</a><br /></td></tr>
<tr class="separator:gadb92679719950635fba8b1b954072695"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa12aedd096506c9639c1581acd5c6a78"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaa12aedd096506c9639c1581acd5c6a78">__REV16</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaa12aedd096506c9639c1581acd5c6a78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gaa12aedd096506c9639c1581acd5c6a78">More...</a><br /></td></tr>
<tr class="separator:gaa12aedd096506c9639c1581acd5c6a78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb695341318226a5f69ed508166622ac"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE int16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gacb695341318226a5f69ed508166622ac">__REVSH</a> (int16_t value)</td></tr>
<tr class="memdesc:gacb695341318226a5f69ed508166622ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gacb695341318226a5f69ed508166622ac">More...</a><br /></td></tr>
<tr class="separator:gacb695341318226a5f69ed508166622ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf944a7b7d8fd70164cca27669316bcf7"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gaf944a7b7d8fd70164cca27669316bcf7">__RBIT</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaf944a7b7d8fd70164cca27669316bcf7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value.  <a href="#gaf944a7b7d8fd70164cca27669316bcf7">More...</a><br /></td></tr>
<tr class="separator:gaf944a7b7d8fd70164cca27669316bcf7"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Variables</h2></td></tr>
<tr class="memitem:gaafcad33f86db3a8e1f55925989f9d2dc"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>sat</b></td></tr>
<tr class="separator:gaafcad33f86db3a8e1f55925989f9d2dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<p>Access to dedicated instructions </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga15ea6bd3c507d3e81c3b3a1258e46397"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">&#9670;&nbsp;</a></span>__BKPT <span class="overload">[1/3]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __BKPT</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;__breakpoint(value)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Breakpoint. </p>
<p>Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga15ea6bd3c507d3e81c3b3a1258e46397"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">&#9670;&nbsp;</a></span>__BKPT <span class="overload">[2/3]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __BKPT</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;bkpt &quot;#value)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Breakpoint. </p>
<p>Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga15ea6bd3c507d3e81c3b3a1258e46397"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga15ea6bd3c507d3e81c3b3a1258e46397">&#9670;&nbsp;</a></span>__BKPT <span class="overload">[3/3]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __BKPT</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;bkpt &quot;#value)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Breakpoint. </p>
<p>Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a id="ga5d5bb1527e042be4a9fa5a33f65cc248"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">&#9670;&nbsp;</a></span>__CLZ <span class="overload">[1/3]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __CLZ&#160;&#160;&#160;__clz</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Count leading zeros. </p>
<p>Counts the number of leading zeros of a data value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>

</div>
</div>
<a id="ga5d5bb1527e042be4a9fa5a33f65cc248"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">&#9670;&nbsp;</a></span>__CLZ <span class="overload">[2/3]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __CLZ&#160;&#160;&#160;(uint8_t)__builtin_clz</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Count leading zeros. </p>
<p>Counts the number of leading zeros of a data value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>

</div>
</div>
<a id="ga5d5bb1527e042be4a9fa5a33f65cc248"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5d5bb1527e042be4a9fa5a33f65cc248">&#9670;&nbsp;</a></span>__CLZ <span class="overload">[3/3]</span></h2>

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          <td class="memname">#define __CLZ&#160;&#160;&#160;(uint8_t)__builtin_clz</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Count leading zeros. </p>
<p>Counts the number of leading zeros of a data value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>

</div>
</div>
<a id="ga671101179b5943990785f36f8c1e2269"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga671101179b5943990785f36f8c1e2269">&#9670;&nbsp;</a></span>__DMB <span class="overload">[1/2]</span></h2>

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          <td class="memname">#define __DMB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><span class="keywordflow">do</span> {\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                   __dmb(0xF);\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                } <span class="keywordflow">while</span> (0U)</div></div><!-- fragment -->
<p>Data Memory Barrier. </p>
<p>Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>

</div>
</div>
<a id="ga671101179b5943990785f36f8c1e2269"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga671101179b5943990785f36f8c1e2269">&#9670;&nbsp;</a></span>__DMB <span class="overload">[2/2]</span></h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __DMB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td>&#160;&#160;&#160;__builtin_arm_dmb(0xF);</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data Memory Barrier. </p>
<p>Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>

</div>
</div>
<a id="ga067d257a2b34565410acefb5afef2203"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga067d257a2b34565410acefb5afef2203">&#9670;&nbsp;</a></span>__DSB <span class="overload">[1/2]</span></h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __DSB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><span class="keywordflow">do</span> {\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                   __dsb(0xF);\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                } <span class="keywordflow">while</span> (0U)</div></div><!-- fragment -->
<p>Data Synchronization Barrier. </p>
<p>Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>

</div>
</div>
<a id="ga067d257a2b34565410acefb5afef2203"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga067d257a2b34565410acefb5afef2203">&#9670;&nbsp;</a></span>__DSB <span class="overload">[2/2]</span></h2>

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          <td class="memname">#define __DSB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td>&#160;&#160;&#160;__builtin_arm_dsb(0xF);</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data Synchronization Barrier. </p>
<p>Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>

</div>
</div>
<a id="gaad233022e850a009fc6f7602be1182f6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaad233022e850a009fc6f7602be1182f6">&#9670;&nbsp;</a></span>__ISB <span class="overload">[1/2]</span></h2>

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      <table class="memname">
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          <td class="memname">#define __ISB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><span class="keywordflow">do</span> {\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                   __isb(0xF);\</div><div class="line">                   __schedule_barrier();\</div><div class="line">                } <span class="keywordflow">while</span> (0U)</div></div><!-- fragment -->
<p>Instruction Synchronization Barrier. </p>
<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>

</div>
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<a id="gaad233022e850a009fc6f7602be1182f6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaad233022e850a009fc6f7602be1182f6">&#9670;&nbsp;</a></span>__ISB <span class="overload">[2/2]</span></h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __ISB</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">void</td><td>)</td>
          <td>&#160;&#160;&#160;__builtin_arm_isb(0xF);</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Instruction Synchronization Barrier. </p>
<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>

</div>
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<a id="gabd585ddc865fb9b7f2493af1eee1a572"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabd585ddc865fb9b7f2493af1eee1a572">&#9670;&nbsp;</a></span>__NOP <span class="overload">[1/3]</span></h2>

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          <td class="memname">#define __NOP&#160;&#160;&#160;__nop</td>
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<p>No Operation. </p>
<p>No Operation does nothing. This instruction can be used for code alignment purposes. </p>

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<a id="gabd585ddc865fb9b7f2493af1eee1a572"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabd585ddc865fb9b7f2493af1eee1a572">&#9670;&nbsp;</a></span>__NOP <span class="overload">[2/3]</span></h2>

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          <td class="memname">#define __NOP&#160;&#160;&#160;__builtin_arm_nop</td>
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      </table>
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<p>No Operation. </p>
<p>No Operation does nothing. This instruction can be used for code alignment purposes. </p>

</div>
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<a id="ga0b13f3617dd4af2cd2eb3a311073f717"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0b13f3617dd4af2cd2eb3a311073f717">&#9670;&nbsp;</a></span>__NOP <span class="overload">[3/3]</span></h2>

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        <tr>
          <td class="memname">#define __NOP</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;nop&quot;)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>No Operation. </p>
<p>No Operation does nothing. This instruction can be used for code alignment purposes. </p>

</div>
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<a id="gab83768933a612816fad669db5488366f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab83768933a612816fad669db5488366f">&#9670;&nbsp;</a></span>__RBIT</h2>

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          <td class="memname">#define __RBIT&#160;&#160;&#160;__builtin_arm_rbit</td>
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      </table>
</div><div class="memdoc">

<p>Reverse bit order of value. </p>
<p>Reverses the bit order of the given value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<a id="ga14f54807872c0f5e05604c4924abfdae"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga14f54807872c0f5e05604c4924abfdae">&#9670;&nbsp;</a></span>__REV <span class="overload">[1/2]</span></h2>

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          <td class="memname">#define __REV&#160;&#160;&#160;__rev</td>
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<p>Reverse byte order (32 bit) </p>
<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

</div>
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<a id="gaca25a02e09983da5558f5242f2f635bc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaca25a02e09983da5558f5242f2f635bc">&#9670;&nbsp;</a></span>__REV <span class="overload">[2/2]</span></h2>

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          <td class="memname">#define __REV</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;__builtin_bswap32(value)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reverse byte order (32 bit) </p>
<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

</div>
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<a id="gad35497777af37e7809271b5e6f9510ba"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad35497777af37e7809271b5e6f9510ba">&#9670;&nbsp;</a></span>__REV16</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __REV16</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gab16acb6456176f1e87a4f2724c2b6028">__ROR</a>(<a class="el" href="group___c_m_s_i_s___core___instruction_interface.html#gadb92679719950635fba8b1b954072695">__REV</a>(value), 16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

</div>
</div>
<a id="gae580812686119c9c5cf3c11a7519a404"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae580812686119c9c5cf3c11a7519a404">&#9670;&nbsp;</a></span>__REVSH</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define __REVSH</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">value</td><td>)</td>
          <td>&#160;&#160;&#160;(int16_t)__builtin_bswap16(value)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

</div>
</div>
<a id="ga95b9bd281ddeda378b85afdb8f2ced86"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga95b9bd281ddeda378b85afdb8f2ced86">&#9670;&nbsp;</a></span>__ROR</h2>

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          <td class="memname">#define __ROR&#160;&#160;&#160;__ror</td>
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</div><div class="memdoc">

<p>Rotate Right in unsigned value (32 bit) </p>
<p>Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">op1</td><td>Value to rotate </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">op2</td><td>Number of Bits to rotate </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>

</div>
</div>
<a id="gaab4f296d0022b4b10dc0976eb22052f9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaab4f296d0022b4b10dc0976eb22052f9">&#9670;&nbsp;</a></span>__SEV <span class="overload">[1/3]</span></h2>

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          <td class="memname">#define __SEV&#160;&#160;&#160;__sev</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Send Event. </p>
<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>

</div>
</div>
<a id="gaab4f296d0022b4b10dc0976eb22052f9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaab4f296d0022b4b10dc0976eb22052f9">&#9670;&nbsp;</a></span>__SEV <span class="overload">[2/3]</span></h2>

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          <td class="memname">#define __SEV&#160;&#160;&#160;__builtin_arm_sev</td>
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      </table>
</div><div class="memdoc">

<p>Send Event. </p>
<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>

</div>
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<a id="gafa58e60fcd2176ad58f96947466ea1fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafa58e60fcd2176ad58f96947466ea1fa">&#9670;&nbsp;</a></span>__SEV <span class="overload">[3/3]</span></h2>

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        <tr>
          <td class="memname">#define __SEV</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;sev&quot;)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Send Event. </p>
<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>

</div>
</div>
<a id="gaac6cc7dd4325d9cb40d3290fa5244b3d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaac6cc7dd4325d9cb40d3290fa5244b3d">&#9670;&nbsp;</a></span>__WFE <span class="overload">[1/3]</span></h2>

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        <tr>
          <td class="memname">#define __WFE&#160;&#160;&#160;__wfe</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Wait For Event. </p>
<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. </p>

</div>
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<a id="gaac6cc7dd4325d9cb40d3290fa5244b3d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaac6cc7dd4325d9cb40d3290fa5244b3d">&#9670;&nbsp;</a></span>__WFE <span class="overload">[2/3]</span></h2>

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          <td class="memname">#define __WFE&#160;&#160;&#160;__builtin_arm_wfe</td>
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      </table>
</div><div class="memdoc">

<p>Wait For Event. </p>
<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. </p>

</div>
</div>
<a id="gaf0330712223f4cfb6091e4ab84775f73"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf0330712223f4cfb6091e4ab84775f73">&#9670;&nbsp;</a></span>__WFE <span class="overload">[3/3]</span></h2>

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        <tr>
          <td class="memname">#define __WFE</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;wfe&quot;)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Wait For Event. </p>
<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. </p>

</div>
</div>
<a id="gad23bf2b78a9a4524157c9de0d30b7448"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad23bf2b78a9a4524157c9de0d30b7448">&#9670;&nbsp;</a></span>__WFI <span class="overload">[1/3]</span></h2>

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          <td class="memname">#define __WFI&#160;&#160;&#160;__wfi</td>
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      </table>
</div><div class="memdoc">

<p>Wait For Interrupt. </p>
<p>Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. </p>

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<a id="gad23bf2b78a9a4524157c9de0d30b7448"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad23bf2b78a9a4524157c9de0d30b7448">&#9670;&nbsp;</a></span>__WFI <span class="overload">[2/3]</span></h2>

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          <td class="memname">#define __WFI&#160;&#160;&#160;__builtin_arm_wfi</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Wait For Interrupt. </p>
<p>Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. </p>

</div>
</div>
<a id="gab28e2b328c4cf23c917ab18a23194f8e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab28e2b328c4cf23c917ab18a23194f8e">&#9670;&nbsp;</a></span>__WFI <span class="overload">[3/3]</span></h2>

<div class="memitem">
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        <tr>
          <td class="memname">#define __WFI</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;__ASM volatile (&quot;wfi&quot;)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Wait For Interrupt. </p>
<p>Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. </p>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a id="gae84a2733711339c5eefeb0d899506b96"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae84a2733711339c5eefeb0d899506b96">&#9670;&nbsp;</a></span>__attribute__() <span class="overload">[1/3]</span></h2>

<div class="memitem">
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          <td class="memname">__attribute__ </td>
          <td>(</td>
          <td class="paramtype">(section(&quot;.rev16_text&quot;))&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<p>Reverse bit order of value. </p>
<p>Unsigned Saturate.</p>
<p>Signed Saturate.</p>
<p>Reverses the bit order of the given value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value</dd></dl>
<p>Saturates a signed value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (1..32) </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value</dd></dl>
<p>Saturates an unsigned value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (0..31) </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gab1ea24daaaaee9c828f90cbca330cb5e">&#9670;&nbsp;</a></span>__DMB()</h2>

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<p>Data Memory Barrier. </p>
<p>Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7fe277f5385d23b9c44b2cbda1577ce9">&#9670;&nbsp;</a></span>__DSB()</h2>

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<p>Data Synchronization Barrier. </p>
<p>Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae26c2b3961e702aeabc24d4984ebd369">&#9670;&nbsp;</a></span>__ISB()</h2>

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<p>Instruction Synchronization Barrier. </p>
<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf944a7b7d8fd70164cca27669316bcf7">&#9670;&nbsp;</a></span>__RBIT()</h2>

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<p>Reverse bit order of value. </p>
<p>Reverses the bit order of the given value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadb92679719950635fba8b1b954072695">&#9670;&nbsp;</a></span>__REV()</h2>

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<p>Reverse byte order (32 bit) </p>
<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa12aedd096506c9639c1581acd5c6a78">&#9670;&nbsp;</a></span>__REV16()</h2>

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<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gacb695341318226a5f69ed508166622ac">&#9670;&nbsp;</a></span>__REVSH()</h2>

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<p>Reverse byte order (16 bit) </p>
<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gab16acb6456176f1e87a4f2724c2b6028">&#9670;&nbsp;</a></span>__ROR()</h2>

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          <td class="paramname"><em>op1</em>, </td>
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<p>Rotate Right in unsigned value (32 bit) </p>
<p>Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">op1</td><td>Value to rotate </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">op2</td><td>Number of Bits to rotate </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga372c0535573dde3e37f0f08c774a3487">&#9670;&nbsp;</a></span>__SSAT()</h2>

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<p>Signed Saturate. </p>
<p>Saturates a signed value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (1..32) </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6562dbd8182d1571e22dbca7ebdfa9bc">&#9670;&nbsp;</a></span>__USAT()</h2>

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          <td class="paramname"><em>val</em>, </td>
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<p>Unsigned Saturate. </p>
<p>Saturates an unsigned value. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (0..31) </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>

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<h2 class="groupheader">Variable Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gaafcad33f86db3a8e1f55925989f9d2dc">&#9670;&nbsp;</a></span>sat</h2>

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<b>Initial value:</b><div class="fragment"><div class="line">{</div><div class="line">  <span class="keywordflow">if</span> ((sat &gt;= 1U) &amp;&amp; (sat &lt;= 32U))</div><div class="line">  {</div><div class="line">    <span class="keyword">const</span> int32_t max = (int32_t)((1U &lt;&lt; (sat - 1U)) - 1U);</div><div class="line">    <span class="keyword">const</span> int32_t min = -1 - max ;</div><div class="line">    <span class="keywordflow">if</span> (val &gt; max)</div><div class="line">    {</div><div class="line">      <span class="keywordflow">return</span> max;</div><div class="line">    }</div><div class="line">    <span class="keywordflow">else</span> <span class="keywordflow">if</span> (val &lt; min)</div><div class="line">    {</div><div class="line">      <span class="keywordflow">return</span> min;</div><div class="line">    }</div><div class="line">  }</div><div class="line">  <span class="keywordflow">return</span> val</div></div><!-- fragment -->
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